1. Field of the Invention
The present invention relates to a method of controlling a semiconductor memory device, for example, a NAND-type flash memory which is applied to a memory card.
2. Description of the Related Art
Recently, a NAND-type flash memory is composed of, for example, a plurality of planes in order to enable high-speed access. Each plane is composed of a memory area which is a memory cell array of a set of a plurality of blocks each including a plurality of pages, a data cache for transmitting/receiving data to/from outside, and a page buffer for receiving and holding data from the data cache. The page is an access unit at a data write/read time, and the block is a data erase unit.
Each plane uses two buffers, that is, the data cache and the page buffer. Thereby, the NAND-type flash memory is enabled to execute a write operation while the controller of the memory card is reading out data from the data cache.
In the meantime, the NAND-type flash memory can erase data only on a block-by-block basis. Even in the case of rewriting data in only one page, it is necessary to erase a block comprising a plurality of pages. In the block that is to be erased, the other pages which are not rewritten need to be copied to another block. The copy of the page is executed in the following manner.
To begin with, data of one page is read out from the NAND-type flash memory into the page buffer. The data in the page buffer is transferred to the data cache, and the transferred data is read out from the data cache to the controller. The read-out data is subjected to, e.g. error correction by the controller. Thereafter, the controller designates a page which is the destination of copy, and delivers the error-corrected data to the data cache in the NAND-type flash memory. The data in the data cache is transferred to the page buffer, and the data in the page buffer is written in the designated page that is the destination of copy.
In this case, in order to realize high-speed data rewrite, it is necessary to increase the speed of the copy operation. In the case where a plurality of copy operations are to be executed, data read-out and data write are repeated in succession. In the NAND-type flash memory, while the controller of the memory card is reading out data from the data cache or while the controller is writing data in the data cache, data can be written from the page buffer into the memory cell. This function of writing data from the page buffer into the memory cell while data is being transferred between the controller and the data cache is referred to as “cache function”. The cache function can increase the speed of the copy operation, compared to the ordinary write operation in which data transfer between the controller and the data cache and data write from the page buffer into the memory cell are separately executed.
This cache function, however, cannot be used unless a block which is the source of copy and a block which is the destination of copy are present within the same plane. For example, if there are many blocks with defects (referred to as “defective blocks”) in a specific plane and there is no empty block, which is a destination of copy, in the plane, it would become impossible to assign a block of the destination of copy in the plane. In such a case, the cache function cannot be used, and the speed of the copy operation decreases. Consequently, there arises a problem that the write speed decreases. Under the circumstances, there has been a demand for a method of controlling a semiconductor memory device, which can avoid the absence of an empty block which is a destination of copy in a specific plane, and can prevent a decrease in write speed.
As related art, the following technique has been developed. For example, a plurality of physical blocks in a NAND-type flash memory are classified into a plurality of groups. If the number of defective blocks in each group is less than a predetermined value, a plurality of blocks which belong to different groups are virtually combined into a virtual block (see, e.g. Jpn. Pat. Appln. KOKAI Publication No. 2003-15947).